U.S. Pat. No. 6,906,940 discloses a three-dimensional memory 100 that has, as shown in FIG. 10, a source plane SP to which source lines connected to the source terminals of memory cells 105 are commonly connected; a drain plane DP to which bit lines connected to the drain terminals of the memory cells 105 are commonly connected; and a word plane WP to which word lines connected to the gate terminals of the memory cells 105 are commonly connected. In the three-dimensional memory 100, the planes SP, DP, WP are perpendicular to one another.
As illustrated in FIG. 10, memory cell arrays 101, 102 etc. are stacked, forming multiple layers, and the source terminals of the memory cells 105 (106) arranged in each memory layer are commonly connected to its associated source plane SP. The source plane SP of the memory layer where a selected memory cell 105 exists is connected to ground potential (0 V). On the other hand, the source planes SP of other memory layers where unselected memory cells exist are kept a floating (F).